This invention relates to a device which can be used as the interface between two separate processors in a multiprocessor system.
In a conventional multiprocessor system, two data processors communicate with each other through a common memory to which they share access. At any given time only one of them can be granted access to this memory which is granted on a first-come, first-served basis. If both processors request access to the memory at the same time only one is granted access immediately and the other must wait until the first processor has completed its access before it can proceed. The decision to grant access to one processor or the other is made by logic embedded in the individual interfaces between the processors and the common memory. When both processors contend for access, the processor which loses the arbitration receives a `not ready` signal from its interface and it must then wait until the `not ready` signal is removed and access is granted. The `not ready` signal typically must be synchronised to the processors' clock to ensure that the specified setting up and hold times are met.
Such a multiprocessor system is becoming of greater importance because a system using several microprocessors can provide enough processing power to compete with a single more powerful and expensive central processing unit. The drawback of the conventional system described above lies in the requirement for numerous device packages to be provided and connected in circuit to accomplish the bus interfacing as described. In addition, if either processor has a private memory connected to its local bus the interface must also include tristate buffers to isolate the local bus from the multiprocessor system bus to prevent accesses to the private memory from interfering with any activity on the multiprocessor bus intiated by the other processor. When timing control circuitry has been added, the hardware requirements for such bus interfaces becomes substantial despite the use of LSI integrated circuits.
The interfaces would be simplified if the common memory were provided as a dual-port RAM, but in such a case a common memory of, say, 256 bytes would occupy 256 address locations in the I/O or memory address space of both processors.